In recent years, the memory requirements for personal computers have greatly increased, including both requirements for increased memory capacity and improved memory access speed. One major reason for the increased memory requirements is the desire of computer users to view graphical images, including three-dimensional graphical images, with high accuracy and detail. Displaying such graphical images requires large amounts of memory to store the graphical data, while regularly updating these images requires high access speeds to that data.
One way of providing improved access speeds is to pipeline memory access requests. A relatively new bus architecture and protocol, known as Accelerated Graphics Port (AGP), has been developed to provide improved memory access speeds between a graphics controller and system memory in a computer system (see Accelerated Graphics Port Interface Specification, Revision 1.0, Intel Corporation, Jul. 31, 1996). FIG. 1 is a functional block diagram that highlights certain portions of a prior art computer system 200 that includes a pipelined memory access architecture such as AGP. A graphics controller 202 is coupled with a system memory 204 via AGP interface circuitry 206 and a memory controller 208. The graphics controller 202 is coupled with a video monitor 210 and controls how graphical images are displayed on the video monitor.
The graphics controller 202 is also coupled with a local frame buffer 212. A portion of the graphics data used to produce graphical images is stored in the local frame buffer 212, while another portion of the graphics data is stored in the system memory 204. Typically, the graphics data stored in the system memory 204 includes texture maps that are models of surface textures that are shared by different images displayed on the video monitor 210. The local frame buffer 212 typically stores other graphics data, such as Z buffers that are used to create three-dimensional graphics images.
The speed at which the graphics controller 202 can display graphical images on the video monitor 210 is limited by the speed at which the graphics controller can access the graphics data from the system memory 204. The AGP interface circuitry 206 provides improved memory access speeds, largely by pipelining memory access requests, and thereby substantially hiding individual memory access times or latencies associated with non-pipelined memory access requests. The AGP interface circuitry 206 includes a request queue 214 that stores a plurality of memory access requests from the graphics controller 202 for subsequent service by the memory controller 208. Each memory access request includes information concerning the type of request (read or write), the address of the location to be accessed in system memory, and the requested data byte length. The AGP interface circuitry 206 also includes a write data queue 216 that stores data associated with write requests residing in the request queue 214. Similarly, the AGP interface circuitry 206 includes a read data return queue 218 that stores data retrieved by the memory controller 208 for subsequent return to the graphics controller 202.
The request queue 214 may include both high priority and low priority requests, which have separate priority and ordering rules. High priority requests are used very infrequently, such as when a request needs immediate processing. Low priority requests represent the large majority of memory access requests, and are the subject of the following discussion. For purposes of brevity, therefore, subsequent reference to read and write requests will be understood to encompass the low priority AGP read and write requests, as one example of ordered pipelined memory access requests.
Service of the pipelined read and write requests is performed in accordance with particular ordering rules dictated by the AGP specification. Read data is returned to the graphics controller 202 in the same order as requested. As a practical matter this rule of read data return is readily accomplished by the memory controller 208 accessing the system memory 204 in the order requested, although such need not be the case. All write requests are, in fact, processed by the memory controller 208 in the order requested by the graphics controller 202. Read data must be coherent with previously issued write requests ("reads push writes"). However, write operations may bypass previously requested read operations, which allows write operations to be combined to minimize the frequency of write operations to the system memory 204.
Allowing write operations to pass read operations means that the request queue 214 does not function strictly as a first-in-first-out (FIFO) buffer, and logic circuitry is then required to point to read and write requests within the request queue. Such logic circuitry can be rather complex and result in significant time delays for any but a relatively small size request queue 214. Thus, the conventional circuitry used to pipeline memory access requests does not take full advantage of the improved access bandwidth afforded, in principle, by request pipelining.